This invention pertains to a semiconductor memory device, e.g., a DRAM (dynamic random access memory) and to a manufacturing method therefor.
For example, with recent DRAMs, various memory capacitor structures have been proposed to maintain the required cell capacitor capacity while reducing the base area of the memory cell capacitor.
Referring to FIGS. 10-14, cross sections of a conventional memory cell transistor section and drain diffusion section are shown, and the manufacturing method therefor will be explained.
First, as shown in FIG. 10a, for example, elements are separated by field oxide film 102, silicon oxide (SiO2) film 104 is formed, as an inter-layer insulating film, over the entire surface of silicon semiconductor substrate 101, on which is formed an access transistor structure, which includes impurity diffusion layer 103, and others, and silicon nitride (Si3N4) film 105 is further formed on that.
Next, as shown in FIG. 10b, contact hole 106 that reaches impurity diffusion layer 103 is formed in silicon nitride film 105 and silicon oxide film 104.
Next, as shown in FIG. 11a, low-resistance polysilicon film 107 is formed over the entire surface to bury contact hole 106.
Next, as shown in FIG. 11b, polysilicon film 107 is etched back, removing all of polysilicon film 107 on silicon nitride film 105 outside of contact hole 106 and leaving contact plug 107 made of this low-resistance polysilicon only in contact hole 106. At this time, to essentially completely remove polysilicon film 107 on silicon nitride film 105, some overetching is applied. Thus, as shown, contact plug 107 is formed slightly depressed from the top edge of contact hole 106.
Next, as shown in FIG. 12a, silicon oxide film 108 is formed over the entire surface.
Next, as shown in FIG. 12b, silicon oxide film 108 is anisotropically etched to form through-hole 109 that reaches contact plug 107.
Next, as shown in FIG. 13a, low-resistance polysilicon film 110 is formed over the entire surface, including the inner surface of through-hole 109.
Next, as shown in FIG. 13b, polysilicon film 110 is etched back, essentially removing all of polysilicon film 110 on silicon oxide film 108 outside of through-hole 109. By doing this, memory capacitor crown-type lower electrode (storage node) 110, made of this low-resistance polysilicon, is formed in through-hole 109.
Next, as shown in FIG. 14a, silicon oxide film 108 is essentially entirely removed by wet etching using an aqueous solution of HF. At this time, silicon nitride film 105 functions as an etching stopper.
Next, as shown in FIG. 14b, capacitor dielectric film 111, composed of, for example, a stacked film of a silicon nitride film and a silicon oxide film (NO composite film), or another high dielectric material, for example, tantalum oxide (Ta2O5), barium strontium titanate (BST), lead zirconate titanate (PZT), etc., is formed to cover the surface of storage node 110, and memory capacitor upper electrode (cell plate) 112, made of a low-resistance polysilicon film, is further formed on that.
A crown-type memory capacitor structure is formed using the above processes.
In recent DRAMs, the length of one side of storage node 110, laterally or longitudinally, has approached approximately the diameter of contact plug 107, to decrease cell size smaller. For this reason, one side of through-hole 109 formed in the process in FIG. 12b is approximately equal to the diameter of contact plug 107, that is, the diameter of contact hole 106. In addition, because of problems with bit line and storage node electric capacitance, silicon nitride film 105 cannot be thickened.
With the conventional manufacturing method discussed above, when contact plug 107 is formed with the process shown in FIG. 11b, it is over-etched, so contact plug 107 is depressed approximately 100 nm from the top edge of contact hole 106. For this reason, as shown in FIG. 15a, contact plug 107 is depressed below silicon nitride film 105, and silicon oxide film 104 is exposed at the side of contact hole 106.
In this state, as shown in FIG. 15b, if the position of through-hole 109 formed in silicon oxide film 108 is off, as shown in FIG. 16a, when silicon oxide film 108 is removed by wet etching after storage node 110 is formed, as shown in FIG. 16b, underlying silicon oxide film 104 is also significantly hollowed out. When upper electrode 112 intrudes into this area, it causes short-circuits and parasitic capacitance.
Because it is impossible to completely eliminate mis-positioning of through-hole 109, when one side of storage node 110 is approximately equal to the diameter of contact plug 107, it is extremely difficult to prevent etching of silicon oxide film 104 beneath it.
So the purpose of this invention is to provide a semiconductor memory device with a contact plug structure that prevents inadvertent etching of an underlying silicon oxide film, even when one side of the storage node is approximately equal to the diameter of the contact plug, in a DRAM such as discussed above, for example, and a manufacturing method therefor.
The semiconductor memory device of this invention, that will solve the aforementioned problems, has a semiconductor substrate provided with an impurity diffusion layer in a prescribed place in the surface region, an insulator layer provided on the aforementioned semiconductor substrate, a contact hole provided in the aforementioned insulator layer in a position on the aforementioned impurity diffusion layer, a contact plug that buries the aforementioned contact hole and that is provided projecting upward above the aforementioned insulator layer, a memory capacitor lower electrode that is provided on the aforementioned insulator layer connected to the aforementioned contact plug, a capacitor dielectric film provided on the surface of the aforementioned lower electrode, and a memory capacitor upper electrode provided on the aforementioned capacitor dielectric film.
With one embodiment of this invention, at least one side of the planar shape of the aforementioned lower electrode is approximately equal to the diameter of the aforementioned contact plug.
With one embodiment of this invention, an indented section is formed in the top surface of the aforementioned lower electrode to constitute a crown-type memory capacitor.
The semiconductor memory device manufacturing method of this invention has a process where a first insulator layer is formed over the entire surface of a semiconductor substrate where an impurity diffusion layer is formed in a prescribed place in the surface region, a process where a second insulator layer is formed over the entire surface of the aforementioned first insulator layer, a process where a third insulator layer is formed over the entire surface of the aforementioned second insulator layer, a process where a contact hole that passes through the aforementioned first through third insulator layers is formed in a position on the aforementioned impurity diffusion layer, a process where a first conductor layer is formed over the entire surface of the aforementioned third insulator layer to bury the aforementioned contact hole, a process where the aforementioned first conductor layer is etched back essentially removing all of the aforementioned first conductor layer on the aforementioned third insulator layer outside the aforementioned contact hole and at the same time leaving the aforementioned first conductor layer projecting upward at least above the aforementioned first insulator layer in the aforementioned contact hole, a process where a fourth insulator layer is formed over the entire surface, including on the aforementioned first conductor layer in the aforementioned contact hole, a process where a through-hole that reaches the aforementioned first conductor layer is formed at least in the aforementioned fourth insulator layer, a process where a second conductor layer is formed over the entire surface including the inner surface of the aforementioned through-hole, a process where the aforementioned second conductor layer is etched back essentially removing all the aforementioned second conductor layer on the aforementioned fourth insulator layer outside the aforementioned through-hole, a process where the aforementioned fourth and third insulator layers are essentially entirely removed, a process where, after the aforementioned fourth and third insulator layers are removed, a fifth insulator layer is formed on the surface of the aforementioned second conductor layer, and a process where a third conductor layer is formed at least on the aforementioned fifth insulator layer.
In addition, the semiconductor memory device manufacturing method based on another embodiment of this invention has a process where a first insulator layer is formed over the entire surface of a semiconductor substrate on which is formed an impurity diffusion layer in a prescribed place in the surface region, a process where a second insulator layer is formed over the entire surface of the aforementioned first insulator layer, a process where a third insulator layer is formed over the entire surface on the aforementioned second insulator layer, a process where a contact hole that passes through the aforementioned first through third isolator layers is formed in a position on the aforementioned impurity diffusion layer, a process where a first conductor layer is formed over the entire surface of the aforementioned third insulator layer to bury the aforementioned contact hole, a process where the aforementioned first conductor layer is etched back essentially entirely removing the aforementioned first conductor layer on the aforementioned third insulator layer outside the aforementioned contact hole while at the same time leaving the aforementioned first conductor layer projecting upward at least above the aforementioned first insulator layer in the aforementioned contact hole, a process where the aforementioned third insulator layer is essentially entirely removed, a process where a fourth insulator layer is formed over the entire surface including the aforementioned first conductor layer, a process where a through-hole that reaches the aforementioned first conductor layer is formed in the aforementioned fourth insulator layer, a process where a second conductor layer is formed over the entire surface including the inner surface of the aforementioned through-hole, a process where the aforementioned second conductor layer is etched back essentially entirely removing the aforementioned second conductor layer on the aforementioned fourth insulator layer outside the aforementioned through-hole, a process where the aforementioned fourth insulator layer is essentially entirely removed, a process where, after the aforementioned fourth insulator layer is removed, a fifth insulator layer is formed on the surface of the aforementioned second conductor layer, and a process where a third conductor layer is formed at least on the aforementioned fifth insulator layer.
In addition, the contact plug structure of this invention is a contact plug for electrically connecting low-resistance layers separated above and below each other with an intervening insulator layer, and the contact plug that is buried in the aforementioned insulator layer is provided projecting upward above the aforementioned insulator layer.